Visa resultat

Electronic system design project, DAT095

Your background

1. My study background is:

Chalmers civilingenjör programme - Electrical Engineering»		9		37%
Chalmers civilingenjör programme - Computer Engineering»		6		25%
Chalmers civilingenjör - other programme»		0		0%
Chalmers högskoleingenjör programme - Electrical Engineering»		1		4%
Chalmers högskoleingenjör programme - Computer Engineering»		0		0%
Chalmers högskoleingenjör - other programme»		0		0%
Other Swedish civingenjör programme»		0		0%
Other Swedish högskoleingenjör programme»		2		8%
Foreign university - Electrical Engineering»		5		20%
Foreign university - Computer Engineering»		1		4%
Foreign university - other programme»		0		0%
Other (explain below)»		0		0%

Genomsnitt: 4

2. What type of team were you a member of?

Analog»		4		16%
Digital»		20		83%

Genomsnitt: 1.83

Cadence circuit simulation
0 svarande

Poor»		0		0%
Less than sufficient»		0		0%
Sufficient»		0		0%
More than sufficient»		0		0%
Good»		0		0%

Genomsnitt: 0

3. (For digital-team members only): Grade your own competence at the beginning of the course

- The ASIC part was by far the hardest part since all we had was a script. If that didin"t work then you couldn"t do much.»
- hardware description and verification, TDA956, taught me VHDL coding other than ad-hoc improvisations used in other courses before. Nothing could prepare me to the weird C-functions of the MB"s "hidden" libraries...»

Software (C programming)
20 svarande

Poor»		3		15%
Less than sufficient»		3		15%
Sufficient»		7		35%
More than sufficient»		1		5%
Good»		6		30%

Genomsnitt: 3.2

Hardware FPGA
20 svarande

Poor»		1		5%
Less than sufficient»		0		0%
Sufficient»		7		35%
More than sufficient»		7		35%
Good»		5		25%

Genomsnitt: 3.75

Hardware ASIC
20 svarande

Poor»		0		0%
Less than sufficient»		11		55%
Sufficient»		6		30%
More than sufficient»		3		15%
Good»		0		0%

Genomsnitt: 2.6

4. (For analog-team members only): Grade your own competence, at the beginning of the course

Analog design
4 svarande

Poor»		1		25%
Less than sufficient»		2		50%
Sufficient»		1		25%
More than sufficient»		0		0%
Good»		0		0%

Genomsnitt: 2

Digital design (transistor level)
4 svarande

Poor»		0		0%
Less than sufficient»		2		50%
Sufficient»		2		50%
More than sufficient»		0		0%
Good»		0		0%

Genomsnitt: 2.5

AD conversion
4 svarande

Poor»		0		0%
Less than sufficient»		2		50%
Sufficient»		2		50%
More than sufficient»		0		0%
Good»		0		0%

Genomsnitt: 2.5

Cadence schematic entry
4 svarande

Poor»		0		0%
Less than sufficient»		1		25%
Sufficient»		3		75%
More than sufficient»		0		0%
Good»		0		0%

Genomsnitt: 2.75

Cadence circuit simulation
4 svarande

Poor»		0		0%
Less than sufficient»		2		50%
Sufficient»		2		50%
More than sufficient»		0		0%
Good»		0		0%

Genomsnitt: 2.5

Your own effort

5. How many hours per week did you spend on this course?

24 svarande

At most 15 hours/week»		3		12%
Around 20 hours/week»		8		33%
Around 25 hours/week»		9		37%
Around 30 hours/week»		3		12%
At least 35 hours/week»		1		4%

Genomsnitt: 2.62

- I was the only one i the group that had a "hour diary". That should have been enforced more.» (Around 20 hours/week)
- sometimes a lot less, sometimes a lot more» (Around 25 hours/week)
- did way more than rest of group..» (Around 25 hours/week)
- The work load was very high at times!» (Around 30 hours/week)
- Much more work required in the end of the project» (Around 30 hours/week)

6. How was your workload divided over the two periods?

Rather evenly over both study periods»		4		16%
More work in period 3 but rather evenly in each period»		4		16%
More work in period 4 but rather evenly in each period»		8		33%
Most work at the end of the two periods»		3		12%
Most work at the of period 4»		5		20%
Other (pls explain below)»		0		0%

Genomsnitt: 3.04

- Run into most problems in period 4» (Most work at the of period 4)
- Period 4 was MUCH harder than period 3.» (Most work at the of period 4)

7. How large part of the teaching offered did you attend?

24 svarande

0%»		1		4%
25%»		1		4%
50%»		3		12%
75%»		11		45%
100%»		8		33%

Genomsnitt: 4

- Did not have time to go to the lectures, even though they seemed interesting the time had to be spent on the project.» (50%)
- They didin"t give much, since you still in the end used the knowledge you had from before» (75%)

8. How many courses other than this one did you take in...

- No other courses, but working 60%»
- »

Period 3?
24 svarande

0»		1		4%
1»		17		70%
2»		6		25%
Other (explain below)»		0		0%

Genomsnitt: 2.2

Period 4?
24 svarande

0»		1		4%
1»		17		70%
2»		5		20%
Other (explain below)»		1		4%

Genomsnitt: 2.25

Goals and goal fulfilment

9. How understandable are the course goals?

I have not seen/read the goals»		8		33%
The goals are difficult to understand»		1		4%
The goals give some guidance, but could be clearer»		8		33%
The goals clearly describe what I am supposed to learn»		7		29%

Genomsnitt: 2.58

- The project goals should have been explanied more, i mean 10us as goal and then only read every 5000 value? really difficult to understand the goal there» (The goals are difficult to understand)

10. Are the goals reasonable considering your background and the number of credits?

18 svarande

No, the goals are set too low»		2		11%
Yes, the goals seem reasonable»		16		88%
No, the goals are set too high»		0		0%

Genomsnitt: 1.88

11. Did the examination assess whether you have reached the goals?

No, not at all»		3		13%
To some extent»		10		45%
Yes, definitely»		5		22%
I don"t know/have not been examined yet»		4		18%

Genomsnitt: 2.45

- pass or fail without much, if any, feedback from any part of the project deliverables, how can I even answer this...» (No, not at all)
- There was very little feedback on the work you had done» (To some extent)
- The tollgates were timel checks but the time distribution was rather uneven» (To some extent)

Teaching and course administration

12. To what extent has the teaching been of help for your learning?

Small extent»		12		52%
Some extent»		8		34%
Large extent»		1		4%
Great extent»		2		8%

Genomsnitt: 1.69

13. What is your opinion of the size of the project task?

Much too small»		0		0%
Somewhat small»		4		16%
Somewhat large»		11		45%
Much too large»		6		25%
Don"t know»		3		12%

Genomsnitt: 3.33

- Would have been more fun to develop a larger system (i.e. mp3 player?) with fewer but bigger groups.» (Somewhat small)
- mostly period 4 consisted of too many reports and presentation which required you too waste much time that could be spent on finishing the project....» (Somewhat large)
- In attempting to cover the entire design cycle, the software phase stretched rather too long» (Somewhat large)
- with more guidance the project would have been easier to grasp» (Much too large)
- Much too large with the competence I had at the beginning of the course» (Much too large)
- good size» (Don"t know)

14. Was the project group size appropriate for the project task?

Too small team for project task»		3		12%
Reasonable match»		17		70%
Too large team for project task»		4		16%
Don"t know»		0		0%

Genomsnitt: 2.04

- Double the group size and maybe the task is possible to complete» (Too small team for project task)
- We where five, and that was a good number» (Reasonable match)
- the number of parallel tasks varied from week to week. Some weeks only 1 person could do something, other weeks all were busy even through out the weekends.» (Reasonable match)

15. How did you find the level of detail of the project specification?

Much too vague»		8		33%
Somewhat too vague»		13		54%
Reasonable»		3		12%
Somewhat too detailed»		0		0%
Much too detailed»		0		0%
Don"t know»		0		0%

Genomsnitt: 1.79

- Many changes and unknowns during the course of the project - frustrating to do one thing and then have to change it because the specs changed.» (Much too vague)
- On some points the specification seemed intentionaly vauge, but it contained so manny points that where not thought through, one had to almost completely ignore it to get a functional product.» (Much too vague)
- It seemed like there were many details that noone had thought about» (Somewhat too vague)
- The specification changed every two weeks, difficult to keep up» (Somewhat too vague)
- some guidline in power consumtion ans size would be nice» (Somewhat too vague)
- it changing alot as the project whent along which is a good thing , and I think its should stay vague» (Somewhat too vague)

16. How do you rate the level of challenge you experienced in the project work?

Very low level»		0		0%
Low level»		1		4%
Medium level»		14		58%
High level»		7		29%
Very high level»		2		8%

Genomsnitt: 3.41

- the challenge of making a pass or fail project with no feedback. Not very challenging, although the time limit and extra suprise presentations pulled it up to medium...» (Medium level)
- There was some unsolved problems that increased the challenge» (High level)
- to many new things without appropiate lectures» (High level)
- The workload was unreal, to few people to complete a task this big.» (Very high level)

17. Did you find the level of challenge that you experienced appropriate in a project like this one?

Too low»		2		8%
OK»		20		83%
Too high»		2		8%

Genomsnitt: 2

- A more complex system would force everyone to become better - but then it has to be backed up with proper teaching!» (Too low)
- with more lectures the challenge will be appropiate» (OK)
- The level of challenge was OK but some lectures after a few weeks of the course about different parts of the design had been good.» (OK)

18. (For digital-team members only): How was your experience using the following EDA tools?

- The biggest problem was that we had no chance to collaborate in the group when working with the EDK, since the windows environment is poorly configured. Also, it used up too much memory and CPU for the computers in the lab, which made everything very time consuming»
- edk full of bugs, ise only uses one core»
- In the end with two courses i could not devote enough time to the place and route and consequently did not take part in that phase actively.»
- did not get to use the asic tools so much»

EDK
20 svarande

Very Poor»		4		20%
Poor»		5		25%
OK»		7		35%
Good»		3		15%
Excellent»		1		5%
Don"t know»		0

Genomsnitt: 2.6

Virtex-II Pro FPGA prototype card
20 svarande

Very Poor»		1		5%
Poor»		0		0%
OK»		5		25%
Good»		8		40%
Excellent»		6		30%
Don"t know»		0

Genomsnitt: 3.9

ModelSim
20 svarande

Very Poor»		0		0%
Poor»		0		0%
OK»		3		15%
Good»		13		65%
Excellent»		4		20%
Don"t know»		0

Genomsnitt: 4.05

Xilinx ISE FPGA P&R tool
20 svarande

Very Poor»		0		0%
Poor»		3		15%
OK»		3		15%
Good»		11		57%
Excellent»		2		10%
Don"t know»		1

Genomsnitt: 3.63

RTL compiler
20 svarande

Very Poor»		0		0%
Poor»		1		6%
OK»		7		43%
Good»		6		37%
Excellent»		2		12%
Don"t know»		4

Genomsnitt: 3.56

SOC Encounter
20 svarande

Very Poor»		1		7%
Poor»		4		28%
OK»		5		35%
Good»		2		14%
Excellent»		2		14%
Don"t know»		6

Genomsnitt: 3

ncsim
20 svarande

Very Poor»		0		0%
Poor»		3		30%
OK»		2		20%
Good»		2		20%
Excellent»		3		30%
Don"t know»		10

Genomsnitt: 3.5

19. (For analog-team members only): How was your experience using the following EDA tools?

Cadence Viruoso schematic entry
6 svarande

Very Poor»		0		0%
Poor»		0		0%
OK»		3		75%
Good»		1		25%
Excellent»		0		0%
Don"t know»		2

Genomsnitt: 3.25

Cadence Viruoso simulation interface to Spectre
5 svarande

Very Poor»		0		0%
Poor»		0		0%
OK»		3		75%
Good»		1		25%
Excellent»		0		0%
Don"t know»		1

Genomsnitt: 3.25

Cadence Virtuoso Layout (lab only)
5 svarande

Very Poor»		1		25%
Poor»		1		25%
OK»		1		25%
Good»		1		25%
Excellent»		0		0%
Don"t know»		1

Genomsnitt: 2.5

20. (For digital-team members only): To what extent has these labs/material been of help for your in your project?

- There was a lot of documentation that we looked up, for example for the divider.»
- Per Larsson-Edefors guide from the methods course was an excellent guide.»
- home pages, and lots and lots of guides dont remember»

EDK lab1
20 svarande

Small extent»		5		25%
Some extent»		10		50%
Large extent»		4		20%
Great extent»		1		5%

Genomsnitt: 2.05

EDK lab2
20 svarande

Small extent»		5		25%
Some extent»		10		50%
Large extent»		5		25%
Great extent»		0		0%

Genomsnitt: 2

RC/Encounter/HCMOS) ASIC flow quick guide
19 svarande

Small extent»		7		36%
Some extent»		5		26%
Large extent»		7		36%
Great extent»		0		0%

Genomsnitt: 2

Other
10 svarande

Small extent»		3		30%
Some extent»		4		40%
Large extent»		3		30%
Great extent»		0		0%

Genomsnitt: 2

21. (For analog-team members only): To what extent has these labs/material been of help for your in your project?

Cadence lab 1 (Schematic entry)
4 svarande

Small extent»		1		25%
Some extent»		2		50%
Large extent»		1		25%
Great extent»		0		0%

Genomsnitt: 2

Cadence lab 2 (Simulation)
4 svarande

Small extent»		1		25%
Some extent»		2		50%
Large extent»		1		25%
Great extent»		0		0%

Genomsnitt: 2

Cadence lab 3 (Layout and verification)
4 svarande

Small extent»		2		50%
Some extent»		2		50%
Large extent»		0		0%
Great extent»		0		0%

Genomsnitt: 1.5

Razavi
4 svarande

Small extent»		1		25%
Some extent»		0		0%
Large extent»		2		50%
Great extent»		1		25%

Genomsnitt: 2.75

Other books
4 svarande

Small extent»		0		0%
Some extent»		1		25%
Large extent»		3		75%
Great extent»		0		0%

Genomsnitt: 2.75

Abo
4 svarande

Small extent»		0		0%
Some extent»		1		25%
Large extent»		3		75%
Great extent»		0		0%

Genomsnitt: 2.75

Other reports
4 svarande

Small extent»		0		0%
Some extent»		1		25%
Large extent»		3		75%
Great extent»		0		0%

Genomsnitt: 2.75

Other scientific papers
4 svarande

Small extent»		0		0%
Some extent»		1		25%
Large extent»		3		75%
Great extent»		0		0%

Genomsnitt: 2.75

22. To what extent has the LIPS project model and the LIPS project manual been helpful to you in the project work?

Low exent»		16		66%
Some extent»		6		25%
Large extent»		2		8%
Great extent»		0		0%

Genomsnitt: 1.41

- Completely useless!» (Low exent)
- Why did we use this? I didn"t give anything!» (Low exent)
- Initialy this was the no.1 source of grief. The model is the worst thing ever created. The teachers did"nt even folow it!, The model specifies that all document management should be done in M$ Word wich we as students don"t have access to or can afford.» (Low exent)
- in the small groups we had, the model was almost never used » (Low exent)
- extremely annoying» (Low exent)
- Caused more troubles than it solved.» (Low exent)
- It slowed us down since we went for the earliest deadline first anyway, and you can"t plan for errors, bugs or requirement specification changes. But it gave us a nice hint on what we had left to do.» (Some extent)
- mostly in the beginning, then we built on that model for second hand in. » (Large extent)

23. (For analog-team members only): In your opinion would a top-down design approach using a high-level simulation language such as Simulink or Verilog A have been beneficial for your project?

Yes»		1		25%
No»		3		75%
Don"t know»		0		0%

Genomsnitt: 1.75

- Introduce Verilog-AMS might be a good idea» (Yes)
- the problem was not to understand how the desging should work but more WHY the design diden´,t work» (No)

24. How well did the course administration, web page, handouts etc work?

Very badly»		4		16%
Rather badly»		12		50%
Rather well»		8		33%
Very well»		0		0%

Genomsnitt: 2.16

- The information was scattered between e-mails, course homepage and presentations.» (Very badly)
- Changes in the last minute, changes to specifications that double the workload.» (Very badly)
- no webpage hardly used it for more than geting new information, on changes made ,» (Very badly)
- The two different homepages were confusing. Also, relevant information didn"t always show up on the homepage» (Rather badly)
- Some stuff here, other stuff there - use EITHER the student portal or an external page, not both!» (Rather badly)
- Use 1 homepage.» (Rather badly)
- What happend to our Wiki?» (Rather badly)
- Course homepage is not good!» (Rather badly)
- spreading news across 2 pages was confusing, but otherwise there was no problem with it» (Rather badly)
- one page is enough.. and don"t write important information in the news section without adding it somewhere else..» (Rather badly)

25. How well did the planning, such as the scheduling of deadlines hand-ins etc work for you?

Very badly»		1		4%
Rather badly»		8		33%
Rather well»		13		54%
Very well»		2		8%

Genomsnitt: 2.66

- Why spend so much time on phase 1a and 1b when all the work is in phase 2a and 2b? The planning of the project was really bad.» (Very badly)
- deadlines where set wrong, to much time in the beginning and to little time at the end» (Rather badly)
- dont change specifications the day before deadline! » (Rather badly)
- became too rushed in the end...too much time on the software phase and too little time for the ASIC P & R» (Rather badly)
- More work moved to lp3 to give more time for ASIC developement.» (Rather badly)
- earliest deadline first, our reports were finished at least a week before their deadlines.» (Rather well)

26. Would you have preferred that the different teams had different project tasks (under the constraint that there would not be more resources for the course overall)?

No»		10		41%
Yes»		7		29%
Don"t know»		7		29%

Genomsnitt: 1.87

- Make all teams work on the same task, but well defined parts instead!» (No)
- Good practice to divide tasks among the group» (No)
- Since you could get help each other solving time consuming non specified problems, such as tool problems.» (No)
- That would have been more fun.» (Yes)

27. There has been requests for more lectures on related topics. This year there were only a few. Here are some suggestions for topics one could include. Mark the ones that would interest you:

(på denna fråga var det möjligt att välja flera svarsalternativ)

Research-related lectures»		6		25%
Industry-related lectures»		19		79%
Electrical issues, such as EMC»		6		25%
Packaging»		4		16%
High-level issues, such as system integration»		14		58%
Efficient coding styles in VHDL»		18		75%
Regulations and standards for electronic products»		5		20%
VHDL code reuse»		15		62%
Design for efficient production»		9		37%
Software-hardware codesign»		14		58%

- Advanced hardware - using and creating multiple clocks. Scanchains in practice (testability).» (Industry-related lectures, Electrical issues, such as EMC, Packaging, High-level issues, such as system integration, Efficient coding styles in VHDL, VHDL code reuse, Software-hardware codesign)
- Efficient coding styles in VHDL! this is a MUST, none of the iesd students have any good grasp on how to organize a larger vhdl project. how comunication between modules work, pos/neg edge.» (Industry-related lectures, High-level issues, such as system integration, Efficient coding styles in VHDL, VHDL code reuse)
- DFM, DFT would be interesting as would emerging design and verification techniques.» (Research-related lectures, Industry-related lectures, High-level issues, such as system integration, VHDL code reuse, Software-hardware codesign)
- A project like this require excellent VHDL knowledge, many in project course simply were not good enough. Better understanding of what hardware your VHDL-code will generate is necessary(maybe something for the introduction course).» (Industry-related lectures, Electrical issues, such as EMC, Efficient coding styles in VHDL, Software-hardware codesign)
- the vhdl coding style "two method guesler" spelling may be wrong , was introduced in the hardware verification course , should be used as a standard for the vhdl part of the project, » (Industry-related lectures, Efficient coding styles in VHDL, Design for efficient production, Software-hardware codesign)
- Analog: Dual rail, switched capacitor circuits etc» ()

Study climate

28. How were the opportunities for asking questions and getting help?

Very poor»		0		0%
Rather poor»		3		12%
Rather good»		14		58%
Very good»		7		29%
I did not seek help»		0		0%

Genomsnitt: 3.16

- There where many opportunities to ask questions, however the help received was minimal» (Rather good)
- Thanks to the lab managers..» (Rather good)
- Always open and friendly, definitely good!» (Very good)
- I did seek help alot,» (Very good)

29. How well has cooperation between you and your fellow students worked?

Very poorly»		0		0%
Rather poorly»		1		4%
Rather well»		16		66%
Very well»		7		29%
I did not seek cooperation»		0		0%

Genomsnitt: 3.25

30. How was the course workload?

Too low»		0		0%
Low»		0		0%
Adequate»		16		69%
High»		5		21%
Too high»		2		8%

Genomsnitt: 3.39

31. How was the total workload for you in...

- Period 4 would have been too high if the other course I took was tougher.»
- programing c, with a hardware processor is easy , hardware works as it should , error finding in vhdl can be hard. »

Period 3?
24 svarande

Too low»		1		4%
Low»		5		20%
Adequate»		11		45%
High»		5		20%
Too high»		2		8%

Genomsnitt: 3.08

Period 4?
24 svarande

Too low»		0		0%
Low»		1		4%
Adequate»		4		16%
High»		15		62%
Too high»		4		16%

Genomsnitt: 3.91

Summarizing questions

32. What is your general impression of the course?

Poor»		3		12%
Fair»		5		20%
Adequate»		11		45%
Good»		5		20%
Excellent»		0		0%

Genomsnitt: 2.75

- The ASIC help was a disaster. Probably why there was no chip produced.» (Poor)
- Not at all what I expected - four versions of the same system! I can see the benefits, but by the third time it gets old.» (Fair)
- Could have been better with better planning.» (Adequate)
- It was a good opportunity to explore the limitations of FPGA and ASIC implementations of a system, which hardly could be gained through anything but experience.» (Adequate)
- very intresting project but more lectures needed om analog parts» (Adequate)
- could have been better planned. For instance clarification in the specification took longer than expected....consequently we did not have implementations that completely matched the specification. The specifications themselves were a little too hazy to begin with.» (Adequate)

33. What should definitely be preserved to next year?

34. What should definitely be changed to next year?

35. Additional comments