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Introduction to Electronic System Design, Lp 1 Ht11, DAT092

Status: Avslutad
Öppen för svar: 2011-10-24 - 2011-11-04
Antal svar: 16
Procent av deltagarna som svarat: 11%
Kontaktperson: Åsa Samdell»

Your own effort

1. How many hours per week did you spend on this course?

We mean total time, that is, it comprises the time you spent in class and the time you spent on your own work. Try to estimate the average time over the entire study period.

16 svarande

At most 15 hours/week»1 6%
Around 20 hours/week»6 37%
Around 25 hours/week»1 6%
Around 30 hours/week»4 25%
At least 35 hours/week»4 25%

Genomsnitt: 3.25

- At the exam week, I spend about 30hours.» (Around 20 hours/week)
- Ridiculous how much time you had to spend on this course compared to every other course I have ever had on Chalmers.» (At least 35 hours/week)
- O my god!!!! WORKLOAD TO HIGH!!!!!» (At least 35 hours/week)

2. How large part of the teaching offered did you attend?

16 svarande

0%»0 0%
25%»0 0%
50%»2 12%
75%»4 25%
100%»10 62%

Genomsnitt: 4.5

- The lectures were not a big occupation of mine really. The VHDL took all my time. » (75%)

Goals and goal fulfilment

The course syllabus states the course goals in terms of learning outcomes, i.e., knowledge, skills and attitudes to be acquired by the student during the course.

3. How understandable are the course goals?

16 svarande

I have not seen/read the goals»4 25%
The goals are difficult to understand»0 0%
The goals give some guidance, but could be clearer»8 50%
The goals clearly describe what I am supposed to learn»4 25%

Genomsnitt: 2.75

4. Are the goals reasonable considering your background and the number of credits?

Answer this this question and the succeeding one, only if you do know the course goals.

13 svarande

No, the goals are set too low»0 0%
Yes, the goals seem reasonable»10 76%
No, the goals are set too high»3 23%

Genomsnitt: 2.23

- Lots of VHDL code to learn in a short space of time.» (No, the goals are set too high)

5. Did the examination assess whether you have reached the goals?

14 svarande

No, not at all»0 0%
To some extent»5 35%
Yes, definitely»6 42%
I don"t know/have not been examined yet»3 21%

Genomsnitt: 2.85

Teaching and course administration

6. To what extent has the teaching been of help for your learning?

16 svarande

Small extent»3 18%
Some extent»9 56%
Large extent»4 25%
Great extent»0 0%

Genomsnitt: 2.06

- Lars was very helpful but when having troubles with the lab it was hard to get help. Alen was helpful but had to help everyone because Sven didn"t help that many students.» (Small extent)
- Were not a lot of teaching when it comes to VHDL.» (Small extent)
- The VHDL lectures were not very well-made.» (Small extent)
- Very good if it comes to the lectures themselves, but not so about VHDL - there the teaching is too little» (Some extent)
- The VHDL-lectures should be lecturing more methods of using VHDL instead of just saying what we should do in the lab (this info we can read in the lab PM. The methods used in VHDL are harder to find)» (Some extent)
- Need more help in the lab.» (Some extent)

7. What percentage of Lars Svensson"s lectures did you attend?

16 svarande

0%»0 0%
25%»0 0%
50%»2 12%
75%»6 37%
100%»8 50%

Genomsnitt: 4.37

- Probably half of the lectures. » (50%)
- I didn"t have time to go on the lectures i missed since the workload with the labs was so huge so we had to skip the lectures in the end of the course just to have a small chance of beeing done with all the labs» (75%)

8. What was your general opinion of Lars Svensson"s lectures?

16 svarande

Poor»0 0%
Fair»1 6%
Adequate»6 37%
Good»9 56%

Genomsnitt: 3.5

- Because it is always about the theory of projects, it seems boring to those have no such experience. » (Adequate)
- Interesting, many real-life examples, » (Good)
- A good lecture speed with a touch of humour keeps you awake.» (Good)
- The lectures I did attend were good and interesting. » (Good)

9. What percentage of Sven Knutsson"s lectures did you attend?

16 svarande

0%»0 0%
25%»1 6%
50%»0 0%
75%»4 25%
100%»11 68%

Genomsnitt: 4.56

- I think I missed one lecture or something of his.» (75%)

10. What was your general opinion of Sven Knutsson"s lectures?

16 svarande

Poor»0 0%
Fair»10 62%
Adequate»6 37%
Good»0 0%

Genomsnitt: 2.37

- Content is not bad, but it should be better related to the labs. Maybe have teaching sessions during lab hours» (Fair)
- More on how to use VHDL to solve specific problems and less on what can be read in the lab PM.» (Fair)
- Sven is not the best teacher and it would be good to have more VHDL lectures later in the course to get help and general guidance about the lasts lab assignments. » (Fair)
- He went trough it very quickly » (Fair)

11. How many of the guest lectures did you attend?

16 svarande

0»0 0%
1»2 12%
2»6 37%
3»8 50%

Genomsnitt: 3.37

- Attended the one about packaging» (1)
- Actually we had 4 guest lectures, and I attend all of them. But in the answers we don"t have "4 times" option.» (3)

12. What was your general opinion of the guest lectures?

16 svarande

Poor»1 6%
Fair»1 6%
Adequate»10 62%
Good»4 25%

Genomsnitt: 3.06

13. What was your previous knowledge of hardware description languages?

15 svarande

None at all»7 46%
One or more VHDL courses at Chalmers»6 40%
One or more VHDL courses elsewhere»2 13%
One or more Verilog courses»0 0%
Active use Verilog or VHDL in industry»0 0%

Genomsnitt: 1.66

- Not VHDL, nor Verilog. But I had work with assembly, BASIC and C for hardware design with microcontroller 8051 and AVR.» (?)
- And industry during summer.» (One or more VHDL courses at Chalmers)
- Attended the synthesis course during the spring. » (One or more VHDL courses at Chalmers)

14. What is your impression about the HDL-design skills you have gained from the lab series?

16 svarande

Insufficient»0 0%
Fair»3 18%
Sufficient»13 81%
Excessive»0 0%

Genomsnitt: 2.81

- I gained skills for sure, but it was really a lot of work, wich I perceive as being too much» (Sufficient)
- I have gained a lot but the lab series is way to big and time consuming. It does not correspond to 7.5 hp during this course it is simply ridiculous. The lab series has to be less time consuming.. Either that or make the lab memos a LOT better. They were not good. They basically said: do this! but did not offer any guidance at all how to solve the assignment. It would be a lot better if the students could get a lot more guidance from the memos instead of havning to ask the tachers the whole time.. » (Sufficient)

15. To what extent has the course literature and other material been of help for your learning?

16 svarande

Small extent»7 43%
Some extent»4 25%
Large extent»5 31%
Great extent»0 0%

Genomsnitt: 1.87

- I think you should not recommend the book so strongly. I never used it and it cost a considerable amount of money.» (Small extent)

16. How well did the course administration, web page, handouts etc work?

16 svarande

Very badly»0 0%
Rather badly»1 6%
Rather well»9 56%
Very well»6 37%

Genomsnitt: 3.31

Study climate

17. How were the opportunities for asking questions and getting help?

16 svarande

Very poor»0 0%
Rather poor»2 12%
Rather good»9 56%
Very good»5 31%
I did not seek help»0 0%

Genomsnitt: 3.18

- An additional teaching assistant in lab would help a lot, since most of the time one had to wait quite a while until somebody was availible for helping» (Rather poor)
- Lars was helpful.» (Rather good)
- Alen were awesome but Sven was not that godd to ask for help. » (Rather good)
- In the AM lab time slot, it was always difficult to get hold of a supervisor for help.» (Rather good)
- Thank"s to Alen.» (Very good)
- Alen is one of the best persons i have ever met. He always helped the students with the labs and it didn"t matter what time it was on the day. He"s a real rock.» (Very good)

18. How well has cooperation between you and your fellow students worked?

16 svarande

Very poorly»1 6%
Rather poorly»2 12%
Rather well»8 50%
Very well»5 31%
I did not seek cooperation»0 0%

Genomsnitt: 3.06

- My labpartner had no experience in VHDL, I did most of the work. » (Very poorly)
- It was hard to find times to work together due to different schedules.» (Rather well)
- My lab partner and I worked individually in the last 3 labs because the VHDL knowledge differed too much.» (Rather well)
- The cooperation between my fellow students worked good with one exception: My actual lab partner.. It is ridiculous that we are assigned lab partners since it the swedish students that have to be like babysitters for them. My partner did not do anything for us and every time I tried working with him we got a lot less done. It is basically a lottery on which lab partner you get. Especially since the workload during this course as extremely high to get stuck with a bad lab partner is extremely frustrating.. » (Rather well)

19. How was the course workload?

16 svarande

Too low»0 0%
Low»0 0%
Adequate»4 25%
High»3 18%
Too high»9 56%

Genomsnitt: 4.31

- Okay, if you have experience in VHDL or Verilog but some people did not and for them the lab"s pace is too high.» (High)
- The last three lab took very long time. We are still not finished with the last lab.» (Too high)
- Lab workload was too high, one really should be able to finsh before exam week» (Too high)
- The VHDl lab series was ridiculous. Did not have time to finish the lab series in time.. And to be forced to explain the assignments I did for my lab partner every time was frustrating..» (Too high)
- To much problems with VHDL-coding.» (Too high)

20. How was the total workload this study period?

16 svarande

Too low»0 0%
Low»1 6%
Adequate»3 18%
High»5 31%
Too high»7 43%

Genomsnitt: 4.12

- The other course was fine but the only reason for the workload being to high during this study period was due to the VHDL lab series which was extremely time consuming.. » (Too high)
- Due to this course.» (Too high)

Summarizing questions

21. What is your general impression of the course?

15 svarande

Poor»0 0%
Fair»2 13%
Adequate»3 20%
Good»9 60%
Excellent»1 6%

Genomsnitt: 3.6

- The high workload made this course frustrating when it could have been fun and educating.. It"s a shame really.. » (Fair)
- To much to do in the labs.» (Fair)

22. What should definitely be preserved to next year?

- Guest lectures, broad approach to the introduction course (including lectures about writing, project managment,...)»
- The vhdl lecture»
- Optional exam keeps the stress low in the exam week.»
- VHDL laboratories»
- Alen and Lars are good.. »
- Guest lectures»
- Alen, he was king.»
- Same style of lectures from Lars and labs as well as the feedback lecture from Alen.»

23. What should definitely be changed to next year?

- It is too much work to reach grade 3. Maybe the last lab should be optional for higher grade. The exam was easy if you had time to study the lecture slides.»
- Less lab work and better teaching about lab contents»
- The lab pm for all labs. And the first 3-4 labs were very easy. The could be much more advanced and maybe start the last 2 labs earlier. »
- The labs (again, sorry). They are too tedious. Maybe divide them in parts and make some parts only for those who want a higher grade. Lab 5 and 6 takes much more time because you have to sit in the lab to solve the problems. Of course we should use real hardware in the course but maybe minimize the task to less error-prone ones and/or tasks that you can simulate at home and be quite sure that your code works. Lab 6 was hard to simulate because I didn"t want to calculate how the samples would look like after passing through a FIR filter with 20-30 taps.»
- there should be more guest lectures on integrated circuit design»
- A lot less comprehensive VHDL lab series so you at least have time to finish on time and not spend double the amount of time we were supposed to spend. »
- Better VHDL lecture.»
- The labs. »
- The pace of the VHDL lectures as they were too fast. Maybe a few more lecture slots to cover the VHDL side of things.»
- In the labs, give a schematic over where all the jumpers shall be on the PCB and how the oscilloscope and signal generator shall be tuned»
- We would suggest that the teachers help students more during the laborations. We didn"t get enouph help from the teachers during the laborations. We had problem in programming VHDL because we did not have a basic knowledge of programming in VHDL. It"s not enouph that the teachers, in the lab, just to see the code and tell us to fix the problem. We did not have enouph time to do and finish all the laborations and we dont know when we will finish them due to that we started new courses now. »

24. Additional comments

- Because my lab partner and my friends" lab partners did not know any VHDL at all we asked Lars if there is a requirement on the international students to have knowledgte in VHDL. He said that there was a requirement for one type of HDL. I spoke to another international student and he DID NOT know of any such requirement. The labs are NOT suited for student who has not done any VHDL. So either change the labs to suit students without VHDL-knowledge or make sure that there is a VHDL requirement that IS FOLLOWED.»
- If the workload for other courses is the same as this one, I would never graduate from Chalmers.»

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