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Introduction to electronic system design, Lp 1 Ht09, DAT091

Status: Avslutad
Öppen för svar: 2009-10-12 - 2009-10-28
Antal svar: 25
Procent av deltagarna som svarat: 51%
Kontaktperson: Åsa Lundgren»

Your Background

1. Rate your previuos VHDL experience, where 5 equals large experience and 1 none

25 svarande

0 0%
2 8%
6 24%
10 40%
7 28%

Genomsnitt: 3.88

- I have taken Dig o Dat 2 on Chalmers. This is the only "VHDL" course that is mandatory for applications to MPIES, though the knowledge from that course was not sufficient to manage this course.» (2)
- I think there should be some extra lectures for VHDL language and for fixed point arithmatic.» (1)

Your own effort

2. How many hours per week did you spend on this course?

We mean total time, that is, it comprises the time you spent in class and the time you spent on your own work. Try to estimate the average time over the entire study period.

25 svarande

At most 15 hours/week»3 12%
Around 20 hours/week»5 20%
Around 25 hours/week»5 20%
Around 30 hours/week»6 24%
At least 35 hours/week»6 24%

Genomsnitt: 3.28

- We were over burnded by the VHDL LAB work. » (At most 15 hours/week)
- That"s a little bit more than I expected, but probably it is related to getting accustomed to study pace (I joined this master program a year after getting bachelors).» (Around 25 hours/week)
- Average value 25h/week. But we still need to continue to finish the lab. Quite impossible to finish it on time.» (Around 25 hours/week)
- In the first three weeks I stayed in school from 9 AM to 11 PM in avarage, I seldom left school before midnight. After three weeks I didn"t have the energy to continue in the same pace. Then I"ve spent about 30 h every week. I have been to school every weekend this semester between 5 and 20 h.» (At least 35 hours/week)

3. How large part of the teaching offered did you attend?

25 svarande

0%»0 0%
25%»0 0%
50%»2 8%
75%»6 24%
100%»17 68%

Genomsnitt: 4.6

- Skipped some due to try to finish labs + assignments in the other course (DICD).» (75%)

Goals and goal fulfilment

The course syllabus states the course goals in terms of learning outcomes, i.e., knowledge, skills and attitudes to be acquired by the student during the course.

4. How understandable are the course goals?

25 svarande

I have not seen/read the goals»3 12%
The goals are difficult to understand»3 12%
The goals give some guidance, but could be clearer»16 64%
The goals clearly describe what I am supposed to learn»3 12%

Genomsnitt: 2.76

- Quite fuzzy.» (The goals are difficult to understand)
- The course is supposed to give some basic view of subject area, so I don"t think there could be really strict goals.» (The goals give some guidance, but could be clearer)

5. Are the goals reasonable considering your background and the number of credits?

Answer this this question and the succeeding one, only if you do know the course goals.

22 svarande

No, the goals are set too low»1 4%
Yes, the goals seem reasonable»14 63%
No, the goals are set too high»7 31%

Genomsnitt: 2.27

- There could be more introduction to common design practices, it would be helpful for course labs too.» (No, the goals are set too low)
- I think the investigating procedure about lab assignment can be made more tighter and removing the examination and making the grades to maximum possible with only this lab exercises. It may include industrial level product design styles to be fallowed.» (Yes, the goals seem reasonable)
- This course is not designed to learn, it"s designed as a display of already acquired knowledge. If you are not well accustomed to VHDL before this course, there is no way to meet the time limit.» (No, the goals are set too high)
- It is impossible for people with no vhdl background to pass the course. That is proven when only two groups finished the labs in time. » (No, the goals are set too high)

6. Did the examination assess whether you have reached the goals?

23 svarande

No, not at all»2 8%
To some extent»9 39%
Yes, definitely»5 21%
I don"t know/have not been examined yet»7 30%

Genomsnitt: 2.73

- Previous examinations seems more about syntax of VHDL and System Design overflow and not lab exercises knowledge.» (No, not at all)
- Again, there isn"t much to assess in an introductory course.» (To some extent)
- The examination does not tests the skills acquired during the complete courses» (To some extent)

7. Was the tasks given in the lab PM:s clear and understandable?

24 svarande

Yes»15 62%
No»9 37%

Genomsnitt: 1.37

- but it still need me a long long time to understand the meaning of it. » (Yes)
- most of them were very time consuming. often there was not enough time to finish them in one session.» (Yes)
- Could be a LOT clearer. Alot of time is spent just trying to understand what you"re really supposed to do.» (No)
- Absolutely not!!!!!!» (No)
- At first I thought we had to use our own components, adders, multipliers and so on in the filters, but apparantly that was not needed. I also did not understand that the first implementation of the adder & multiplier was to simply use the "+" and "*" operators in VHDL and spent many hours on implementing them i other ways.» (No)
- There was almost no information about the tasks and part of the information was incorrect.» (No)
- Sometime descriptions where not very clear, but teaching assistants always provided needed amount of explanation.» (No)
- I often needed more precise questions, more precise informations. And some help (on reading material) for the difficults parts.» (No)
- Missing important information» (No)
- The preparatory exercises were very fussy. They may be crystal clear to someone who have been working in the industry with VHDL, but not to me. It would also be good to clearly inform the students that they are supposed to finish the lab before the lab-slot, which served as a Q & A and examination session. This was realized after the first lab, then it already was to late to catch up, you were one week behind schedule.» (No)

Teaching and course administration

8. To what extent has the teaching been of help for your learning?

25 svarande

Small extent»10 40%
Some extent»8 32%
Large extent»6 24%
Great extent»1 4%

Genomsnitt: 1.92

- Not really anything. There were only a few lectures and they didn"t really say much.» (Small extent)
- Difficult to see the "red line" in the teaching. Quite different subjects, difficult to see what was supposed to be on the exam.» (Small extent)
- None, the lectures and labs had nothing related to each other. There was one or 2 lectures about the labs in the start but they gave nothing since all they said stood already on the slides. A lecutures with 100+ slides is worthless. But the slide could be used as references during the labs.» (Small extent)
- Could get some help in the lab. No useful info on the lectures.» (Small extent)
- The VHDL lectures were hard to melt. The guest lectures were very nice and also the lectures on project management.» (Small extent)
- It is pretty hard to under stand anything when the teacher has to click thou 200 slides in one session. And skip most of the slides. » (Small extent)
- Good overview of electronic system design but not enough on VHDL/Labs.» (Some extent)

9. Were the course lectures a touch too many?

25 svarande

Yes»9 36%
No»16 64%

Genomsnitt: 1.64

- In a way, yes. Many of the lectures were quite alike and said the same thing. I guess half of the lectures can be summed in the words "Everything is too complex to understand." A few more lectures in VHDL would be nice...» (Yes)
- But there should be more lectures about VHDL and less about project management and other stuff.» (No)
- Need more lectures for vhdl not project management or something like that» (No)
- Good lectures in general.» (No)
- Skip the VHDL lectures though and use the time either for labs or a more methods oriented lecture.» (No)
- But could have been more related to VHDL/Labs.» (No)
- More VHDL lessons.» (No)

10. What do you think about the way of teaching VHDL?

- acutally i think the teaching time about vhdl is so limited and it"s hard to follow and hard to write the code just a few days after learn it.»
- The first assignment should also be compulsory because it is most important due to syntax. Also duration of lectures should be increased. Also every syntax should be teach with an example of VHDL code.»
- it should be just in lab and the lecture would be related only for vhdl»
- VHDL lectures should be more and also more basic.»
- it is very hard to understand the vhdl syntax/structure by only watching the slides. vhdl lectures can be so much better if they were taught in a computer classroom.»
- the labs are helpful to learn VHDL »
- Bad. We have to learn everything by ourselves basically.»
- To few lectures about actually programming VHDL and to fast pace for those who have never seen VHDL or HDL"s before.»
- too bad »
- Some more information of what real happen in the hardware when you write VHDL would be good. Give more insight how to make efficient hardware.»
- before doing the lab, study a large number of good examples maybe more helpful»
- What teaching of VHDL? There was none. Just pointing at code samples doesn"t give me anything. I would prefer if the VHDL lectures begun at a bit lower level and advanced a bit slower, the lectures which we had started at a higher level and didn"t advance at all.»
- They did not teach VHDL, one lecture when they just showed 100+ slides with vhdl is not a lecture...»
- It was good in the sense that the learning was fast given the short time(particularly foccused towards the lab work). But I believe a good amount of emphasis should be placed on synthesis details, optimization or good coding practices for FPGA"s since that is difficult for us to pick by ourself from the wild.»
- There was no "teaching" as in "having specific class hours to teach VHDL" (except maybe one lecture in the beginning, which only brought an overview of the language), but I think this is the only true way --- students should be able to learn new tools by themself and only require teacher intervention for some really non-obvious matters.»
- Difficult when you"ve never seen VHDL. Need more study material for each lab.»
- Maybe it can not be taught..Pracital experience is crucial.»
- Very bad. Only two lectures. »
- The labs should be much much shorter with one or two tasks that captures the essence of the topics that we are supposed to learn. Now we had up to about six tasks on each lab. Perhaps lab six could be optional, designed for higher grades.»
- The complete VHDl Lecture was given in one class. More VHDl lectures are required.»
- the way of teaching is good and understandable but but it should be in more details.basically we do not the basics of vhdl.»
- Not that good. Too much in too few lectures.»
- Not good. Not much teaching. »

11. Are any more lectures required for the understanding of lab procedures?

25 svarande

Yes»16 64%
No»9 36%

Genomsnitt: 1.36

- As mentioned before.» (Yes)
- To hard labs for those with no VHDL/signal processing background» (Yes)
- Se comments above.» (Yes)
- Also the first lab could have involved handling the hardware and loading and running a pre written program(by the instructor, this should have given some more confidence and feel for writing code for the FPGA.» (Yes)
- A thorough review of the lab would help.» (Yes)
- The lectures presenting the labs were quite good, but strangely placed. For example the three first labs (!!!) where explained at the same time, before the first lab. It would be much better if the lab for a week was presented in the beginning of that week or late the week before.» (No)
- I feel that a lecture is required for handling of signed, fixed and floating point numbers.» (No)

12. Do you think more study material is required for labs?

25 svarande

Yes»18 72%
No»7 28%

Genomsnitt: 1.28

- Some material regarding fixed point arithmatic should be available.» (Yes)
- not necessarily but I feel that a lot of confusion in the first few labs was the inability to think of HDL as something different from sequential programming. Like for instance the idea of a process or a signal or concurrency is not always well established in our thinking mind.» (Yes)
- Some "tips and tricks" material would be nice to have. But detailed underlying concepts should be left for another course (I hope, during DAT110 course they will be highlighted).» (Yes)
- Now there was nothing to help. You got to figure out everything yourself.» (Yes)
- With this high ambition level for the labs, course specific material is required. A book that comprise common pitfalls and useful tricks.» (Yes)
- Yes some more lectures concerning the labs.» (Yes)
- I think there needs to be more lectures regarding the labs.» (No)

13. Where the lab timings too short for the given tasks to be completed in one slot?

24 svarande

Yes»23 95%
No»1 4%

Genomsnitt: 1.04

- the time of the lab was not too short but we didnt have much time as new student to do 2 labs in one day» (?)
- Yes. These should be increased» (Yes)
- By far too short. You have to start the labs several days before the slot and you still don"t finish in time.» (Yes)
- especially the lab5&6 we need the board to finish the lab, but only 4 hours are hard to implement the lab well» (Yes)
- Is this a joke? What during the course was called "labs" were in fact not labs. They were home assignments. There were absolutely NO way the labs could be finished in one slot.» (Yes)
- Yes! It was impossible to finish in one slot, if i had spend about 20+ hours on the lab BEFORE i got there then i may be able to actually finish it but not likely» (Yes)
- Sometime we encountered problems that really needed time. The range of problems was quite wide --- from task understanding to tools configuration. But there was nothing really hard.» (Yes)
- Definitely too short, need at least double... At least...» (Yes)
- 4h is not enough, although if you where very well prepared.» (Yes)
- It was something of a bad joke. about 20 h lab sessions would be more reasonable. and the number of assistants would have to be the double at least, I attended a few lab sessions were I didn"t even get to ask the assistants a single question since they were to busy. By the way, most of the time only one assistant was in the lab.» (Yes)
- The LAB timings are not enough. It takes minimum 12 hours to complete the LAB» (Yes)
- Should have been three or at least two lab slots with TAs each week to get guidence.» (Yes)
- Maybe it should be more pionted out that the most of the work for the labs are supposed to be done before the lab session.» (No)

14. To what extent has the course literature and other material been of help for your learning?

25 svarande

Small extent»4 16%
Some extent»16 64%
Large extent»4 16%
Great extent»1 4%

Genomsnitt: 2.08

- None» (Small extent)
- When the tempo is this high in a course, the literature needs to be very condensed, thus internet forums were the most common source of knowledge.» (Small extent)
- The slides helped a bit I guess.» (Some extent)
- Don"t think the course literature is a good VHDL book.» (Some extent)

15. How well did the course administration, web page, handouts etc work?

25 svarande

Very badly»1 4%
Rather badly»2 8%
Rather well»13 52%
Very well»9 36%

Genomsnitt: 3.2

- The naming of lecture-slides are way off, give lecture number/date and/or real content. not bird.pfd et.c. or just put them in subfolders» (Rather well)
- PingPong is ok but Studentportalen is better from a students point of view.» (Rather well)
- The feedback and the course administration is excellent» (Very well)

Study climate

16. How were the opportunities for asking questions and getting help?

25 svarande

Very poor»3 12%
Rather poor»4 16%
Rather good»8 32%
Very good»9 36%
I did not seek help»1 4%

Genomsnitt: 3.04

- Just one lab slot for asking questions a week is too little.» (Very poor)
- Had to wait long for help in the lab. Perhaps more lab teacher.» (Very poor)
- To few assistants during the lab sessions, and no access to the lab, was no good combination.» (Very poor)
- The people in the lab are good but too few or the time to short.» (Rather poor)
- Too few lab slots and sometimes hard for the assistants to have time for everyone.» (Rather poor)
- the lab teacher could be more explicit when answering questions.» (Rather good)
- need more Student assistants in labs» (Rather good)
- long waiting time during labs» (Rather good)
- Often the lab assistants get "stuck" with students for 15-20+min and it takes long time to get help» (Very good)
- Everybody was very nice and helpful. Of course, there were some unanswered questions, but assistant cannot be blamed for that, because it really requires time to get full context of question. Most of the clues they could give in limited amount of time actually worked in one way or another.» (Very good)

17. How well has cooperation between you and your fellow students worked?

24 svarande

Very poorly»2 8%
Rather poorly»5 20%
Rather well»7 29%
Very well»9 37%
I did not seek cooperation»1 4%

Genomsnitt: 3.08

- i think we should have a larger group not just 2 persons, sometimes i did a lot...» (Very poorly)
- Try to pair up groups more evenly, It"s better for people of the same knowledge background to work together.» (Rather poorly)
- My lab partner did not show up on the lab sessions.» (Rather poorly)
- Rather poorly in the begining. Rather well in the end...» (Rather well)
- I really liked this "Swede/foreigner" partnering scheme (maybe that"s because I had a good partner). It really helps with spoken Swedish skills improvement. :) But it seems that many students were too shy to decide about finishing lab assignments together in spare time. I saw only few groups working together after labs, that"s probably why so many people didn"t finish labs in time.» (Very well)

18. How was the course workload?

25 svarande

Too low»0 0%
Low»0 0%
Adequate»5 20%
High»9 36%
Too high»11 44%

Genomsnitt: 4.24

- Tasks weren"t that hard as many people thought, it was mostly organization issue.» (High)
- That is the labs are too time consuming, takes away a lot of time from the parallell course.» (Too high)
- The so called labs took way too much time.» (Too high)
- Insane, even when i had 80% energy on this course and 20% on the other i was not even near at finish the labs in time.» (Too high)
- Way to high. It is not fair to the other course that the students have no time to work with.» (Too high)

19. How was the total workload this study period?

25 svarande

Too low»0 0%
Low»0 0%
Adequate»7 28%
High»8 32%
Too high»10 40%

Genomsnitt: 4.12

- More you plan to do, more you succeed to do. Nothing is wrong with having high workloads.» (Adequate)
- And this course is the reason for that.» (Too high)
- Se comment above» (Too high)
- Hade no time for the other course» (Too high)
- Since this course had about 100 percent workload and the other course (Digital IC Design) was a standard 50 percent course, the workload was very high.» (Too high)

Summarizing questions

20. What is your general impression of the course?

25 svarande

Poor»4 16%
Fair»4 16%
Adequate»8 32%
Good»8 32%
Excellent»1 4%

Genomsnitt: 2.92

- The so called labs destroy everything.» (Poor)
- Well the lectures was okey but they had nothing to do with the labs.» (Poor)
- I don"t want to do that in my working life. I just took it to have an overview of electronic design. And to know a little bit about VHDL.» (Fair)
- Good labs for those with propper background, for those lacking in VHDL I assume it have been to hard.» (Good)
- That was a nice introduction. Helped to refresh some stuff and accustom myself for later study.» (Good)

21. What should definitely be preserved to next year?

- less workload»
- The labs questions»
- just focus on lab»
- The extra VHDL lecture given at the start of the course.»
- working with a partner in the lab.»
- labs »
- guest lectures and the structure outside VHDL.»
- Required lab preparations with a strict deadline before the lab, really good.»
- Lars Kollberg»
- labs and VHDL, guest lectures particularly future trends and challenges»
- Lab partnering scheme (local student/international student). Guest lectures (I really liked the speaker from ST-Ericsson).»
- Guest lectures. »
- Lab assignments»
- Pass the course for the lab work»
- Guest lectures»
- VHDL labs.»
- The guest lectures.»

22. What should definitely be changed to next year?

- larger group to do the lab»
- The lab and examination should be merged only to lab.»
- remove extra lectures and give time for lab»
- More VHDL lectures must be introduced. If this is not done, then the number of labs can be reduced to even out.»
- a previous and more intense pre lab workshop.»
- the number of lab supervision sessions should be increased »
- Maybe one lab less at least? And more lectures on the labs and VHDL.»
- way more basic VHDL, not just one "lab0" maybe part it into one easy basic VHDL course (max grade 3) for beginners and a harder one for the rest. Again, make it easier for beginners it was tough for me who know a bit of VHDL.»
- labs need to be changed maybe a project based labs will be good»
- The lecture series needs to be reworked, if you want us to learn VHDL, teach VHDL! Quite a few of the lectures said almost the same thing, but then a few stood out from the group. And then the so called labs. The most important change that needs to be done is to rename them from labs to home assignments or something similar. lab 2 and 3 were the by far most time-consuming and many people really got stuck with them, they defenitely need to be made less complex. I"ve also heard from students from last year that the problem was present already then.»
- The labs, There could be shorter labs or more time or more help, or better lectures and so on.»
- Project management - Though very useful, it is very generic and repetitive with other programmes. Considering the valuble industry experience that the instructors carry a very detailed study of large real projects like Bluetooth, mobile platforms or chip design or even a hypothetical problem - like for example setting up a chip design shop in N.Korea. This I believe will help students understand and appreciate the challenges and understand practices and limitation of the real world. Also this could help transfer the knowledge of this mystic and closed industry.»
- Many people wrote very messy and unmaintainable code --- there should be more introduction to best practices. It will really help people to save their time.»
- Improve labs. »
- Lecture parts range should be not that wide.»
- 6 labs is to many, reduce»
- Lab sessions»
- Reduce the Lab course work. Extra burden sometimes refrains from studying. Give extra lectures on handling of fixed, floating point numbers, filter implementation»
- basically many people do not have any idea about vhdl so my opinion is to give brief idea about vhdl programming by taking extra lectures.»
- More lab slots each week.»
- More VHDL lessons »

23. Additional comments

- good guest lectures, very interesting, especially the pacemaker one from Lund. It would be interesting with good/bad design cases aswell.»
- Have access to lab time, other than lab time. And it would need more lab room, because it is always busy.»
- This course has pretty much caused my interest for VHDL to vanish. I am tired of it.»
- time duration is to less for completing tasks. we should get brief idea about lab which we are going to perform in next week i mean how we should do our tasks in labs. »
- The implementation of a filter/AD-DC-interface for the FPGA I think was too much trouble compared to what you actually learned. It felt like it was just a huge amount of time wasted on getting the communication with the ADC and DAC to work properly. »

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