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Visa resultatHär kan se resultatet från utvärderingen och exportera statistiken till ett annat program. Det går också att göra en enkel filtrering genom att klicka på svarsalternativen och kommentarerna eller en avancerad filtrering genom att använda knappen längst ned.
Electronic system design project, Lp4 Vt09, DAT095Status: AvslutadÖppen för svar: 2009-05-18 - 2009-06-03 Antal svar: 29 Procent av deltagarna som svarat: 15% Kontaktperson: Åsa Lundgren»
Your Background1. My study background is:29 svarande
Genomsnitt: 7.34 - Electronics Engineering» (Foreign university - other programme) 2. What type of team were you a member of?29 svarande
Genomsnitt: 1.48 3. (For digital-team members only): Grade your own competence at the beginning of the courseMatrisfrågaSoftware (C-programming)
Genomsnitt: 3.71 Hardware FPGA
Genomsnitt: 3.6 Hardware ASIC
Genomsnitt: 2.73 4. (For analog-team memebers only): Grade your own competence, at the beginning of the courseMatrisfrågaAnalog design
Genomsnitt: 3.2 Digital design (transistor level)
Genomsnitt: 3.53 AD conversion
Genomsnitt: 2.93 Cadence schematic entry
Genomsnitt: 3.66 Cadence circuit simulation
Genomsnitt: 3.4 Your own effort5. How many hours per week did you spend on this course?We mean total time, that is, it comprises the time you spent in class and the time you spent on your own work. Try to estimate the average time over the entire study period.29 svarande
Genomsnitt: 3.17 - A lot» (At least 35 hours/week) 6. How was your workload divided over the two periods?29 svarande
Genomsnitt: 2.62 - more in sp 4» (Most work at the end of the two periods) 7. How large part of the teaching offered did you attend?29 svarande
Genomsnitt: 4.31 8. How many courses other than tis one did you take in period 3 and period 4?MatrisfrågaPeriod 3?
Genomsnitt: 2.34 Period 4?
Genomsnitt: 2.14 Goals and goal fulfilmentThe course syllabus states the course goals in terms of learning outcomes, i.e., knowledge, skills and attitudes to be acquired by the student during the course.9. How understandable are the course goals?29 svarande
Genomsnitt: 3.41 10. Are the goals reasonable considering your background and the number of credits?Answer this this question and the succeeding one, only if you do know the course goals.29 svarande
Genomsnitt: 1.96 - An abstract is provided and then it is expected that we"ll get a chip at the end.» (No, the goals are set too high) 11. Did the examination assess whether you have reached the goals?29 svarande
Genomsnitt: 2.86 - I believe that not every person in my group had a sufficient understanding of the design.» (No, not at all) Teaching and course administration12. To what extend has the teaching (including lab teaching) been of help for your learning?29 svarande
Genomsnitt: 2.62 - Lena is very helpful and good at explaining things but unfortunately also very busy.» (Great extent) 13. What is your opinion of the size of the project task?27 svarande
Genomsnitt: 2.92 - Adequate » (?) 14. Was the project group size appropriate for the project task?29 svarande
Genomsnitt: 2.17 - Five persons for the analog team is a bit too much.» (Reasonable match) 15. How did you find the level of detail of the project specification?29 svarande
Genomsnitt: 2.68 - inputs and outputs cant be specified detailed enough!» (Somewhat too vague) 16. How do you rate the level of challenge you experienced in the project work?29 svarande
Genomsnitt: 3.34 17. Did you find the level of challenge that you experienced appropriate in a project like this one?29 svarande
Genomsnitt: 1.82 - Ok for me but not for all group members.» (OK) 18. (For digital-team members only): How was your experience using the following EDA tools?Matrisfråga- Left soc to the others» EDK
Genomsnitt: 3.71 Virtex-II Pro FPGA prototype card
Genomsnitt: 4.14 ModelSim
Genomsnitt: 4.28 Xilinx ISE FPGA P&R tool
Genomsnitt: 4 RTL compiler
Genomsnitt: 3.64 SOC Encounter
Genomsnitt: 3.14 ncsim
Genomsnitt: 3.57 19. (For analog-team members only): How was your experience using the following EDA tools?Matrisfråga- Cadence is a bit buggy and lengthy.» Cadence Viruoso schematic entry
Genomsnitt: 4 Cadence Viruoso simulation interface to Spectre
Genomsnitt: 3.8 Cadence Virtuoso Layout and verification (DRC, LVS)
Genomsnitt: 3.46 20. (For digital-team members only): To what extent has these labs/material been of help for your in your project?Matrisfråga- Lab PM from Methodes » EDK lab1
Genomsnitt: 2.78 EDK lab2
Genomsnitt: 2.78 RC/Encounter/HCMOS) ASIC flow quik guide
Genomsnitt: 2.53 Other
Genomsnitt: 2.5 21. (For analog-team members only): To what extent has these labs/material been of help for your in your project?Matrisfråga- Maloberti is a good complement for Abo.» Cadence Lab 1,2,3 (Schematic entry, Similation and Layout and vericiation)
Genomsnitt: 3.06 Razavi
Genomsnitt: 2.33 Other books
Genomsnitt: 2.4 Abo
Genomsnitt: 3.26 Other reports
Genomsnitt: 2.28 Other scientific papers
Genomsnitt: 2.73 22. How well did the course administration, web page, handouts etc work?29 svarande
Genomsnitt: 3.27 - some stuff from sp3 disapeared in sp4» (Rather well) 23. How well did the planning, such as the scheduling of deadlines hand-ins etc work for you?29 svarande
Genomsnitt: 3.06 - The schematic design deadline is a bit harsh.» (Rather badly) 24. Would you have preferred that the different teams had different project tasks (under the constraint that there would not be more resources for the course overall)?28 svarande
Genomsnitt: 1.96 - One learn so much more when you can discuss the assignment between groups» (No) 25. There has been requests for more lectures on related topics. This year there were only a few. Here are some suggestions for topics one could include. Mark the ones that would interest you29 svarande(på denna fråga var det möjligt att välja flera svarsalternativ)
- A lecture where the basics of differential circuits and how to "think" about then would be great. » () Study climate26. How were the opportunities for asking questions and getting help?29 svarande
Genomsnitt: 3.34 27. How well has cooperation between you and your fellow students worked?29 svarande
Genomsnitt: 3.44 - Some group members lacked the required prerequisites and others was very hard to work with since they didn"t answer mails or show up in time for the meetings.» (Rather poorly) 28. How was the course workload?29 svarande
Genomsnitt: 3.51 29. How was the total workload for you in the period 3 and period 4?MatrisfrågaPeriod 3?
Genomsnitt: 3.68 Period 4?
Genomsnitt: 3.72 Summarizing questions30. What is your general impression of the course?29 svarande
Genomsnitt: 3.86 31. What should definitely be preserved to next year?- The flow between phase 1 and phase 2 must keep. In phase 1 the design must be tested in FPGA and in phase 2 design must be implemented with ASIC. »- FPGA base system Design ASIC design» - The system where the student is forced to find most of the answers to the design issues him self in papers etc. » - Lena with her abstract style!!!» - general it"s ok» - project specification» - The project groups are intentionally mixed up with Swedish students and International students, this is the best part that we finally had a very good chance to work together with Swedish students, exchange our experience and thoughts, even become friends. This is great!! » - All of step should be preserved, because very important for practical experience.» - seems to be good wat they have igven during the project» 32. What should definitely be changed to next year?- subject must be changed.»- asic ohase should be shifted a litte bit back in quarter 3» - much clear Specfications needed.» - number of member in a team: should be at most 4 the relation between phase 1 and phase 2 need to be better: some parts of the design can"t be used or have to change when in phase 2 due to the difference in system specification between 2 phases!» - project schedual» - At the beginning of Q4, it wasn"t schedule quite well. a few weeks wasted on thinking about how to modify the spec from phase 1 then adapted to ASIC. I think this arrangement between phase 1 and phase 2 should be done earier, then the test group can have more time working on the test-benches and everything would not be pushed to the deadline so hard. The spec of phase 1.c does not really make sense. We didn"t really understand why we have to convert all c-coded user interface down to VHDL, Which is also useless in phase 2. » - I think at beginning of the project that teach should explain more detail to students, because maybe some of them never do the work like this leading them hardly starting.» - the feedback, improvement and how a particular team is processing should be come to act as soon as possible so that they can know what the team is facing» 33. Additional comments- The subject could be more interesting like designing a very basic cpu. CPU could read the instructions and data from a outside chip so the task could be designing the most efficient pipeline structure. That would be more interesting and students would learn much about computer architecture.»
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