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Introduction to electronic system design, HT2008, DAT091Status: AvslutadÖppen för svar: 2008-10-16 - 2008-11-01 Antal svar: 54 Procent av deltagarna som svarat: 81% Kontaktperson: Lena Peterson» Utbildningsprogram studenten tillhör: Elektroteknik 300 hp
Your background1. My study background is:54 svarande
Genomsnitt: 7.59 - Automation and Mechatronics» (Chalmers civilingenjör - other programme (explain below)) 2. I am currently enrolled in this master programme:54 svarande
Genomsnitt: 1.64 - I have different courses from different masters (Erasmus student)» (Not enrolled in master programme) 3. I have previously studied the following hardware design languages:54 svarande
Genomsnitt: 2.55 - And a little Verilog.» (VHDL only) 4. I have previously studied digital filters:54 svarande
Genomsnitt: 2.62 - only studied but never designed.» (Only very little) Your own effort5. How many hours per week did you spend on this course?We mean total time, that is, it comprises the time you spent in class, in the lab and the time you spent on your own work. Try to estimate the average time over the entire study period.54 svarande
Genomsnitt: 3.38 - Mostly trying to accomplish the labs. I was really slow to learn VHDL + understand how to accomplish the labs» (Around 25 hours/week) 6. How large part of the teaching offered did you attend?Matrisfråga - i attended almost all the lecs but was very irrelevent to the course aim and boring in a sense that it didnt helped me in gaining any thing thats y usually went to sleep after 25mins and used to woke up when break was announced» Lectures related to labs
Genomsnitt: 4.24 Other lectures including guest lectures
Genomsnitt: 3.82 7. How many hours did you study to prepare for the final exam?54 svarande
Genomsnitt: 6.05 - VHDL labs took all the time so no time to study other lecture material» (<10) 8. How many other courses did you take this period?54 svarande
Genomsnitt: 2.27 - 3» (Other (explain below)) Goals and goal fulfilmentThe course syllabus states the course goals in terms of learning outcomes, i.e., knowledge, skills and attitudes to be acquired by the student during the course.9. How understandable are the course goals?53 svarande
Genomsnitt: 2.69 - It was made clear to me the last weeks exactly how this course was planned out, with the VHDL and the lectures being 2 "cources".» (The goals give some guidance, but could be clearer) 10. Are the goals reasonable considering your background and the number of credits?Answer this this question and the succeeding one, only if you do know the course goals.47 svarande
Genomsnitt: 2.12 - I think, a master"s level student should know what an asic,fpga is, why power consumption is important, and should have read the paper written by Moore.» (No, the goals are set too low) 11. Did the examination, including the labs, assess whether you have reached the goals?49 svarande
Genomsnitt: 2.24 - Some of the guest lecture is tough to understand.» (To some extent) Teaching and course administration12. To what extent has the teaching (including lectures, labs etc) been of help for your learning?52 svarande
Genomsnitt: 2.07 - i didnt found any help from the lab instructors as their way of talking and accent were hard to under stand also i never picked up what they wanted to say due to their "english". but thanks to my swede lab mate who helped me to understand vhdl. » (Small extent) 13. To what extent did the lectures help you learning?53 svarande
Genomsnitt: 1.81 - Absence of some guide of VHDL for new student.
Because labs are difficult to some extent. » (Small extent) 14. How was the subject coverage of the lectures ?53 svarande
Genomsnitt: 2.49 - The guest lecturers from companies were in fact a very good opportunity. The lecture from Ericsson was perfect. However the microsoft lecture was bad. The aim of that lecture was clear (alternatives to vhdl in a more abstract view such as .NET,C,C++) but the lecturer spent so much time on microsoft products.» (They covered too little material) 15. To what extent did the labs help your learning?52 svarande
Genomsnitt: 2.53 - Because the labs covered so much there was no time for reflection or going into depth.» (Small extent) 16. How was the coverage of the lab exercises?52 svarande
Genomsnitt: 2.61 - Lab 4,5 and 6 were all focused on SPI. Instead of using ICs such as ADC and DAC, we could write a simple IC. These labs were like pic programming with vhdl.» (They covered too little) 17. Was your background in VHDL sufficient?51 svarande
Genomsnitt: 1.76 - NO EXPERIENCE IN VHDL .....» (?) 18. Was your background in digital filters sufficient?51 svarande
Genomsnitt: 2.07 - NO BACKGROUND ON DIGITAL FILTERS» (?) 19. To what extent has the course literature and other material been of help for your learning?52 svarande
Genomsnitt: 1.88 - did not buy the book. help documents for labs could have been more extensive.» (Small extent) 20. How well did the course administration, web page, handouts etc work?52 svarande
Genomsnitt: 3.03 Study climate21. How were the opportunities for asking questions and getting help?52 svarande
Genomsnitt: 3.07 - During the labs, mr Kolberg was very helpful, but mr . Knutsson was not.» (Rather poor) 22. How well has cooperation between you and your fellow students worked?52 svarande
Genomsnitt: 3.07 - I was not able to get much help from my lab partner for VHDL labs which affected my lab performance» (Rather poorly) 23. How was the course workload?51 svarande
Genomsnitt: 4.05 - Very uneven depending on the labs.» (High) 24. How was the total workload this study period?52 svarande
Genomsnitt: 3.96 Summarizing questions25. What is your general impression of the course?52 svarande
Genomsnitt: 2.78 - A good course to learn about VHDL, but many of the lectures seemed very shallow, as is usual with introductory courses» (Poor) 26. What should definitely be preserved to next year?- lab session content. It is very good though a little bit fast for those who did not have background in VHDL. Some guest lectures are ok, give us more vision on trends of system design nowadays. However our background seems not enough to understand all these lectures!»- I think on class, professor should give more examples of VHDL to students. Because abesence of guide for new language is time consume for students. As result, they have no time to understand well the contents of course. » - lab 4 to 6» - the lectures, lab structure» - Labs, guest lectures (very good and intressting) » - Thought provoking lab exercises, which introduce undiscovered ideas and fundamentals.» - labs but the getting started in vhdl lecs needs to be more more more improved.» - lab sessions are really helpful for learning or improving VHDL sklls.» - VHDL Lab work» - Do CONCENTRATE ON VERILOG WHICH IS HIGHLY RECOGONIZED ....CAN GIVE SIMILARITIES OR RELATION TO VHDL AND VERILOG ....FOR EG: WHAT USED AND WHAT NOT USED IN VERILOG AND VHDL ... » - Labs» - VHDL labs» - Labs with some minor changes, Guest lectures.» - The entire project in the labs.» - Lab series from 1 to 5 (not 6)» - the lab contents» - Labs, but less load» - The guest lecturers (not all of them) from industry. They provide their own view (better if not biased too much)» - Some handouts should be accessible beside presentation files. I mean just a print of ppt files are not enough, please add some notes.» - The guestlectures» - the guest lectures» - the lab» - lectures (ordinary and guest)» 27. What should definitely be changed to next year?- The last lab, number 6, a few extra pages in the pm describing the process of going from the system generator to a xilinx project would be good, or perhaps precise reading instructions pointing out relevant sections in the documentation for the software being used. »- the way you teach VHDL. It is quite fast for those who did not familiar with it. Some examples and home assignment to pratice VHDL are need, of course with careful guidances, I think.» - I think the structure of course is very good.» - more vhdl lectures» - the number of labs, especially for the basics. special labs for those who have no background with VHDL. » - Maybe some how make the labs smaller. Have a lectre on Matlab DSP tool. A lecture on digital filters.» - Every one is not interested in DSP so VHDL programming should also be used for some other tasks like ALU or some other processor functions.» - Lab exercises that do not fully correlate to things learnt in the class room.» - the course lecs. need to be more techanical rather than just theoritical.» - Should be given more support or guideline for the VHDL labs» - Cover more details of Lab work in lectures» - 1-2 more lectures on vhdl plz» - DO CONECENTRATE MORE ON THEOROTICAL RELATED TO CODING ...AND GIVE HOME ASSIGNMENTS (PRFERABLY VERILOG) SIMILAR TO DIGITAL DESIGN ....BEING HARWARE LANGUAGE (SO CALLED NOT SOFTWARE)...DO TEACH IMPORTANCE OF HOW THE HARDWARE IS REALIZED ...ETC .. » - Guest lectures should be changed into more studies about the labs.» - Some case studies should be introduced to put things in context» - I think that the VHDL Labs were too complicated. There are a lot of different students with different background. My background was so poor that I did like very much this course because I was lost most of the time. For example, there is a gap of work between Lab2 and Lab3 and I think we are not well prepare for the level of technical work which is ask for by teachers.» - The course should be more focused. It seems that this course is still in the trial phase and is not very mature. Better lectures for VHDL coding and synthesis.» - Nothing.» - In my Bahcelor"s Degree study I always interested with Microcontrollers and Microprocessors, I didn"t have any vhdl or verilog background but after completing all the lab series now I am really get used to VHDL and I clearly understand the background of the hardware design languages. But I think that something going wrong with the lecture.Because before starting the lab series I think first of all Student must understand how VHDL code is synthesised because VHDL is not a assembly or a computer language your code doesn"t like a microcontroller assembly code or a C program you directly code the hardware so before sarting VHDL I think someone must know basic things about which code creates which kind of hardware,after that He can write a reasonable vhdl code so before vhdl brush-up lesson I think there should be a lesson which explains the sysnthesis of the VHDL.» - the subject of the guest lecture» - Reduce the lab workload, please!» - More lectures of the labs. This year the first three labs were presented during 30 minutes and the last three during one lecture. Not sufficient!» - The lab is very hard» - The labs are not defined well. I could not really understand what is required from me from labs and prelabs in complete detail. There were always some things that are required but not told us to do. If you look this from the one of the project models ie, waterfall, the specifications were not set completely and we were discovering that at the very end. Thus we had to sometimes even iterate from the very beginning. Some kind of Wavefrom can be added to do lab documents to show how the designs should act.» - Lab structure should change completely. It was a useless lab.» - The labs, better labmemos are needed. Smaller labs doesnt mean that you learn less.» - labs workload» - There should be some part related to high frequency PCB as every electronics system design has to be implemented on a PCB.» - as i told above,and get from most classmates,the course was based on assuming that the participents have good knowledg of VHDL,but most didn"t!so if there would be additional introduction on vhdl it would be very good!» - some guest lecture should be changed» - u can have good lectures on digital filters & VHDL learning. LAB6 is very hard,when i"ve designed the MATLAB file and generate code for ISE , i haden"t any idea what"s this file.just some friends come to me and help me,the funny thing is no one know why we should change something in ISE AMTLAB FILES. » - Excesive workload in the labs. More information to do the labs.» - The labs.» 28. Additional comments- I am happy for learning some useful knowledges.»- General outline of professional coding could help us.» - Some of the guest lectures are really inspiring. but I couldn"t get most of the idea. some of the information are not for a new student without knowing much of this field, it could be really helpful for an experienced designer but too soon for me.» - NEED TO BE CHANGED IN THIS COURSE ..RATHER THAN ASSIGNING LABS IN SHORT PERIOD OF TIME ...DO GIVE SOME HOME ASSIGNMENTS ...ETC .. » - Lectures was very interesting, but too theoric. Most of the time, after a lecture, I had a lot of idea, but it was very figurative ...» - There was a file that you put up on the course home page that was about "clock enables" and that file really helped me to get on the right track for synthesis. It would have been nice if we had more of those to suggest tips and tricks for synthesizable code.» - the course cover too much subjects that I am a little confused.» - Coordinate the work load with the other course in the study period.» - You"ve got the right idea and solution to a problem with students with different backgrounds. Teach everyone up to a base point and then we can work from that. The lectures are fine and doesn"t have to be changed. I"ll adress the labs as a completly different cource. The PM should have clearer instructions and or give more hints on to solve the problems. More feedback HAS to be given to solutions and this has to be fixed with more people getting involved with the labs. With comprehensive feedback learning will be faster and students wont be stuck on problems from earlier labs. I"m not the best but not a bad student and I had at times 1-3 labs to review at once when they got done. There"s very hard to find faults with a design when you"re just learning and I would like to have the option to send code for review and then get feedback after each of the labs if you didn"t finish. Looking at code is hard work and this has to be adressed with more people working with the labs more than Sven and Lars. Great was that the labs was open at all times and that you had the option to use the Sparta cards even on weekends and evenings (it was needed) one sunday we were 12 people there working on the same lab at late afternoon... I would look over how many people acctually finished the labs on the appointed time and you will get an indication where there was problems. Good luck» - The labs were too crowded and noisy. There were only two people (prof. Sven Knuttson and prof. Lars Kollberg) and they could not help us most of the time when we had a question, and in fact as professors they should not bother with every small question students ask. There should be some TAs helping there. But in anyways the definition of the labs should be better.» - I had the feeling that the lab sessions are good just for a few number of students.»
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