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Introduction to electronic system design, HT2008, DAT091

Status: Avslutad
Öppen för svar: 2008-10-16 - 2008-11-01
Antal svar: 54
Procent av deltagarna som svarat: 81%
Kontaktperson: Lena Peterson»
Utbildningsprogram studenten tillhör: Elektroteknik 300 hp

Your background

1. My study background is:

54 svarande

Chalmers civilingenjör programme - Electrical Engineering»8 14%
Chalmers civilingenjör programme - Computer Engineering»2 3%
Chalmers civilingenjör - other programme (explain below)»3 5%
Chalmers högskoleingenjör programme - Electrical Engineering»0 0%
Chalmers högskoleingenjör programme - Computer Engineering»0 0%
Chalmers högskoleingenjör - other programme (explain below)»0 0%
Other Swedish civilingenjör programme (explain below)»0 0%
Other Swedish högskoleingenjör programme (explain below)»1 1%
Foreign university - Electrical Engineering»28 51%
Foreign university - Computer Engineering»5 9%
Foreign university - other programme (explain below)»5 9%
Other (explain below)»2 3%

Genomsnitt: 7.59

- Automation and Mechatronics» (Chalmers civilingenjör - other programme (explain below))
- Electronic Engineering» (Chalmers civilingenjör - other programme (explain below))
- Automation och mekatronik -Z» (Chalmers civilingenjör - other programme (explain below))
- electronic engineering» (Foreign university - other programme (explain below))
- Mechatronics» (Foreign university - other programme (explain below))
- Communication Engineering» (Foreign university - other programme (explain below))
- Industrial Systems and Industrial Computering» (Foreign university - other programme (explain below))
- Electronical Engineering» (Foreign university - other programme (explain below))
- Foreign University - Electronics Engineering» (Other (explain below))

2. I am currently enrolled in this master programme:

54 svarande

Integrated Electronic System Design»42 77%
Communication Engineering»5 9%
Microtechnology»1 1%
Biomedical Engineering»1 1%
Other master programme»0 0%
Not enrolled in master programme»5 9%

Genomsnitt: 1.64

- I have different courses from different masters (Erasmus student)» (Not enrolled in master programme)

3. I have previously studied the following hardware design languages:

54 svarande

VHDL only»20 37%
Verilog only»9 16%
VHDL and Verilog»1 1%
None»23 42%
Other (explain below):»1 1%

Genomsnitt: 2.55

- And a little Verilog.» (VHDL only)
- just prgramming languages like codevision,assembly» (None)
- C, visual basic» (Other (explain below):)

4. I have previously studied digital filters:

54 svarande

Extensively»3 5%
Some»23 42%
Only very little»19 35%
Not at all»9 16%
Don"t know»0 0%

Genomsnitt: 2.62

- only studied but never designed.» (Only very little)

Your own effort

5. How many hours per week did you spend on this course?

We mean total time, that is, it comprises the time you spent in class, in the lab and the time you spent on your own work. Try to estimate the average time over the entire study period.

54 svarande

At most 15 hours/week»4 7%
Around 20 hours/week»11 20%
Around 25 hours/week»14 25%
Around 30 hours/week»10 18%
At least 35 hours/week»15 27%

Genomsnitt: 3.38

- Mostly trying to accomplish the labs. I was really slow to learn VHDL + understand how to accomplish the labs» (Around 25 hours/week)
- Just an estimate, But it took a lot of time!» (Around 30 hours/week)

6. How large part of the teaching offered did you attend?


- i attended almost all the lecs but was very irrelevent to the course aim and boring in a sense that it didnt helped me in gaining any thing thats y usually went to sleep after 25mins and used to woke up when break was announced»
- missed one lab lecture»

Lectures related to labs
53 svarande

0%»2 3%
25%»5 9%
50%»2 3%
75%»13 24%
100%»31 58%

Genomsnitt: 4.24

Other lectures including guest lectures
52 svarande

0%»2 3%
25%»11 21%
50%»4 7%
75%»12 23%
100%»23 44%

Genomsnitt: 3.82

7. How many hours did you study to prepare for the final exam?

54 svarande

<10»7 12%
10-20»10 18%
20-30»4 7%
30-40»3 5%
40-50»1 1%
50-60»2 3%
60-70»4 7%
70-80»2 3%
>80»1 1%
I have not studied for it yet so I don"t know»14 25%
I did not/do not intend to take the exam»6 11%

Genomsnitt: 6.05

- VHDL labs took all the time so no time to study other lecture material» (<10)
- Had the lectures pretty fresh in my mind, I just went through them once more.» (<10)
- Most of the time I tried to figure out what the guest lecturers are saying. Such as the person from Microsoft who basically show how to use .NET and told that Microsoft Visual Studio is a main stream software so like everybody IC designers should use it. However the lectures given by people from Chalmers were good and were telling what a master"s level student in electronics engineering should already know.» (60-70)
- It will probably be about 10 hours» (I have not studied for it yet so I don"t know)
- i dont know yet from where to prepare and how but any how am planning to spent approx 20hrs over it.» (I have not studied for it yet so I don"t know)
- I intend to study around 25 hours» (I have not studied for it yet so I don"t know)
- will take exam in january because i was busy at the time of exam» (I did not/do not intend to take the exam)

8. How many other courses did you take this period?

54 svarande

2 3%
38 70%
11 20%
Other (explain below)»3 5%

Genomsnitt: 2.27

- (Other (explain below))
- (Other (explain below))
- I took 3 courses this quarter» (Other (explain below))

Goals and goal fulfilment

The course syllabus states the course goals in terms of learning outcomes, i.e., knowledge, skills and attitudes to be acquired by the student during the course.

9. How understandable are the course goals?

53 svarande

I have not seen/read the goals»8 15%
The goals are difficult to understand»9 16%
The goals give some guidance, but could be clearer»27 50%
The goals clearly describe what I am supposed to learn»9 16%

Genomsnitt: 2.69

- It was made clear to me the last weeks exactly how this course was planned out, with the VHDL and the lectures being 2 "cources".» (The goals give some guidance, but could be clearer)
- my expectations from this course was more. i preferred that the course include more lectures in VHDL. But in this course we spend a tiny amount of time in VHDL and the quality of lectures was so poor. I individually didn’,t have major problem in VHDL but I saw lots of student that at the end of labs they didn’,t know essential things in VHDL such as assigning signals 2 times to 1 signal in process. » (The goals give some guidance, but could be clearer)

10. Are the goals reasonable considering your background and the number of credits?

Answer this this question and the succeeding one, only if you do know the course goals.

47 svarande

No, the goals are set too low»6 12%
Yes, the goals seem reasonable»29 61%
No, the goals are set too high»12 25%

Genomsnitt: 2.12

- I think, a master"s level student should know what an asic,fpga is, why power consumption is important, and should have read the paper written by Moore.» (No, the goals are set too low)
- Estimating the goals from what have been taught » (Yes, the goals seem reasonable)
- Hard to be the judge of this, I"ve not worked as hard as labs ever before. Still there needs to be quite a lot of content to get everyone to a good level of knowledge of VHDL.» (Yes, the goals seem reasonable)
- actually the goals were reasonable but for me with no background of VHDL lab sessions were too difficult to deal with,i think it would be better if more introduction to VHDL will be given in the course.» (Yes, the goals seem reasonable)

11. Did the examination, including the labs, assess whether you have reached the goals?

49 svarande

No, not at all»8 16%
To some extent»28 57%
Yes, definitely»6 12%
I don"t know/have not been examined yet»7 14%

Genomsnitt: 2.24

- Some of the guest lecture is tough to understand.» (To some extent)

Teaching and course administration

12. To what extent has the teaching (including lectures, labs etc) been of help for your learning?

52 svarande

Small extent»13 25%
Some extent»25 48%
Large extent»11 21%
Great extent»3 5%

Genomsnitt: 2.07

- i didnt found any help from the lab instructors as their way of talking and accent were hard to under stand also i never picked up what they wanted to say due to their "english". but thanks to my swede lab mate who helped me to understand vhdl. » (Small extent)
- These lectures were not good (in my opinion): Lectures of Sven on Lab Lecture of Arne» (Large extent)

13. To what extent did the lectures help you learning?

53 svarande

Small extent»20 37%
Some extent»23 43%
Large extent»10 18%
Great extent»0 0%

Genomsnitt: 1.81

- Absence of some guide of VHDL for new student. Because labs are difficult to some extent. » (Small extent)
- if there would have been any ""no extent"" option, i have selected that.» (Small extent)
- We had a guest lecturer from computer science of chalmers whom gave us some data for synthesizing. It was pretty good. I think it well be better if our lectures give us specific knowledge not a general information about all things. » (Some extent)

14. How was the subject coverage of the lectures ?

53 svarande

They covered too little material»11 20%
About right»17 32%
They covered somewhat too much material»15 28%
They covered much too much material»8 15%
Don"t know/did not attend»2 3%

Genomsnitt: 2.49

- The guest lecturers from companies were in fact a very good opportunity. The lecture from Ericsson was perfect. However the microsoft lecture was bad. The aim of that lecture was clear (alternatives to vhdl in a more abstract view such as .NET,C,C++) but the lecturer spent so much time on microsoft products.» (They covered too little material)
- More VHDL was needed» (They covered too little material)
- But could be better organized.» (About right)
- too much too wide, but shallow!» (They covered somewhat too much material)
- the course just flew over my head.» (They covered much too much material)

15. To what extent did the labs help your learning?

52 svarande

Small extent»9 17%
Some extent»10 19%
Large extent»29 55%
Great extent»4 7%

Genomsnitt: 2.53

- Because the labs covered so much there was no time for reflection or going into depth.» (Small extent)
- Labs are good. But some difficult for new students.» (Large extent)
- I hadn"t synthesized HDL code before and now I have. I love practical work!» (Large extent)
- You learne a lot from the labs, since you are forced to do a lot of work at home.» (Large extent)
- Lab assistants weren’,t good. It seems that in this lab we need some peoples who are professional in VHDL such as LENA in VLSI lab, she was expert in cadence and VLSI. Those guys weren’,t as useful as I expected. If we had a problem ,we must solved it ourselves. » (Large extent)

16. How was the coverage of the lab exercises?

52 svarande

They covered too little»8 15%
The covered about the right amount»19 36%
They covered somewhat too much»12 23%
They covered much too much»11 21%
Don"t know»2 3%

Genomsnitt: 2.61

- Lab 4,5 and 6 were all focused on SPI. Instead of using ICs such as ADC and DAC, we could write a simple IC. These labs were like pic programming with vhdl.» (They covered too little)
- more guidance (through lab pm and such) would help the understanding of the subject. the current form encouraged too much "hacking"» (They covered too little)
- The labs seemed poorly planned, especially the later ones.» (The covered about the right amount)
- The labs were simply too extensive. There was no chance of going into depth on any assignment. The mandatory pre-lab assignments were not even close to enough as preparation. We basically had to prepare the entire lab in advance (could take 10 hours), and then we would probably make it in time at the lab opportunity. » (They covered much too much)

17. Was your background in VHDL sufficient?

51 svarande

Not at all sufficient»20 39%
Not sufficient»23 45%
Sufficient»8 15%

Genomsnitt: 1.76

- we never learnt vhdl rather i have background in verilog» (Not at all sufficient)
- I have no previos knowledge of VHDL and the lecture of VHDL was to fast and not enogh.» (Not at all sufficient)
- I had none, but previous programming experience so it was quite easy to pick it up.» (Not sufficient)
- I had simulation background but not synthesis.» (Not sufficient)
- I know verilog but I had no idea of the syntax of vhdl spent lots of time correcting those mistakes. such as ELSE IF is written as ELSIF. And you have to put THEN after each IF. There numerous data types in which you have to switch in between them continuously.» (Sufficient)

18. Was your background in digital filters sufficient?

51 svarande

Not at all sufficient»13 25%
Not sufficient»21 41%
Sufficient»17 33%

Genomsnitt: 2.07

- Even though filters were used in the labs, it did not feel like any deeper knowledge on the subject was needed.» (Sufficient)

19. To what extent has the course literature and other material been of help for your learning?

52 svarande

Small extent»18 34%
Some extent»22 42%
Large extent»12 23%
Great extent»0 0%

Genomsnitt: 1.88

- did not buy the book. help documents for labs could have been more extensive.» (Small extent)
- I used "VHDL för konstruktion", a good book.» (Large extent)

20. How well did the course administration, web page, handouts etc work?

52 svarande

Very badly»1 1%
Rather badly»6 11%
Rather well»35 67%
Very well»10 19%

Genomsnitt: 3.03

Study climate

21. How were the opportunities for asking questions and getting help?

52 svarande

Very poor»1 1%
Rather poor»13 25%
Rather good»21 40%
Very good»15 28%
I did not seek help»2 3%

Genomsnitt: 3.07

- During the labs, mr Kolberg was very helpful, but mr . Knutsson was not.» (Rather poor)
- I don"t ask much, but I should!» (I did not seek help)

22. How well has cooperation between you and your fellow students worked?

52 svarande

Very poorly»3 5%
Rather poorly»7 13%
Rather well»25 48%
Very well»17 32%
I did not seek cooperation»0 0%

Genomsnitt: 3.07

- I was not able to get much help from my lab partner for VHDL labs which affected my lab performance» (Rather poorly)
- I like teamwork but honestly don"t know how to do it. Me and my partner worked together but I did most of the coding.» (Rather poorly)
- Cooperation with my lab partner does not fit here, cause he did know anything regarding the subject, and he never made an attempt to learn. Right from the first lab, the lab preparations and executing the codes where all done only by me and he was just a spectator, Cause of which i felt that the subject load was little high. Cooperation with other students was pretty good. Few helped me a lot. » (Rather well)
- if my lab mate havnt helped me understanding vhdl i would be at lab 2 at the moment while we have finished with 4labs and i hope remaining 2 labs would be over in a week after exams.» (Very well)

23. How was the course workload?

51 svarande

Too low»0 0%
Low»0 0%
Adequate»13 25%
High»22 43%
Too high»16 31%

Genomsnitt: 4.05

- Very uneven depending on the labs.» (High)
- The labs were particularly time-consuming.» (Too high)
- The labs was to big, and i spend a lot of time on the labs.» (Too high)
- because of too little guidance.» (Too high)

24. How was the total workload this study period?

52 svarande

Too low»0 0%
Low»0 0%
Adequate»17 32%
High»20 38%
Too high»15 28%

Genomsnitt: 3.96

Summarizing questions

25. What is your general impression of the course?

52 svarande

Poor»8 15%
Fair»13 25%
Adequate»16 30%
Good»12 23%
Excellent»3 5%

Genomsnitt: 2.78

- A good course to learn about VHDL, but many of the lectures seemed very shallow, as is usual with introductory courses» (Poor)
- The concepts taught should already be known by a master"s level student. The labs should be redesigned.» (Fair)
- Took too much time. Had no private life at all. Stressed me up too much. The evaluations of the labs were unfair since some groups got their solutions acknowledged and while others did not even though they had similar solutions.» (Adequate)
- My VHDL coding style has been improved, besides, I"ve got deeper insight into the digital filters.» (Good)
- It is shortcut for me to familiar with VHDL and Digital filter. Those are very helpful for me.» (Excellent)

26. What should definitely be preserved to next year?

- lab session content. It is very good though a little bit fast for those who did not have background in VHDL. Some guest lectures are ok, give us more vision on trends of system design nowadays. However our background seems not enough to understand all these lectures!»
- I think on class, professor should give more examples of VHDL to students. Because abesence of guide for new language is time consume for students. As result, they have no time to understand well the contents of course. »
- lab 4 to 6»
- the lectures, lab structure»
- Labs, guest lectures (very good and intressting) »
- Thought provoking lab exercises, which introduce undiscovered ideas and fundamentals.»
- labs but the getting started in vhdl lecs needs to be more more more improved.»
- lab sessions are really helpful for learning or improving VHDL sklls.»
- VHDL Lab work»
- Labs»
- VHDL labs»
- Labs with some minor changes, Guest lectures.»
- The entire project in the labs.»
- Lab series from 1 to 5 (not 6)»
- the lab contents»
- Labs, but less load»
- The guest lecturers (not all of them) from industry. They provide their own view (better if not biased too much)»
- Some handouts should be accessible beside presentation files. I mean just a print of ppt files are not enough, please add some notes.»
- The guestlectures»
- the guest lectures»
- the lab»
- lectures (ordinary and guest)»

27. What should definitely be changed to next year?

- The last lab, number 6, a few extra pages in the pm describing the process of going from the system generator to a xilinx project would be good, or perhaps precise reading instructions pointing out relevant sections in the documentation for the software being used. »
- the way you teach VHDL. It is quite fast for those who did not familiar with it. Some examples and home assignment to pratice VHDL are need, of course with careful guidances, I think.»
- I think the structure of course is very good.»
- more vhdl lectures»
- the number of labs, especially for the basics. special labs for those who have no background with VHDL. »
- Maybe some how make the labs smaller. Have a lectre on Matlab DSP tool. A lecture on digital filters.»
- Every one is not interested in DSP so VHDL programming should also be used for some other tasks like ALU or some other processor functions.»
- Lab exercises that do not fully correlate to things learnt in the class room.»
- the course lecs. need to be more techanical rather than just theoritical.»
- Should be given more support or guideline for the VHDL labs»
- Cover more details of Lab work in lectures»
- 1-2 more lectures on vhdl plz»
- Guest lectures should be changed into more studies about the labs.»
- Some case studies should be introduced to put things in context»
- I think that the VHDL Labs were too complicated. There are a lot of different students with different background. My background was so poor that I did like very much this course because I was lost most of the time. For example, there is a gap of work between Lab2 and Lab3 and I think we are not well prepare for the level of technical work which is ask for by teachers.»
- The course should be more focused. It seems that this course is still in the trial phase and is not very mature. Better lectures for VHDL coding and synthesis.»
- Nothing.»
- In my Bahcelor"s Degree study I always interested with Microcontrollers and Microprocessors, I didn"t have any vhdl or verilog background but after completing all the lab series now I am really get used to VHDL and I clearly understand the background of the hardware design languages. But I think that something going wrong with the lecture.Because before starting the lab series I think first of all Student must understand how VHDL code is synthesised because VHDL is not a assembly or a computer language your code doesn"t like a microcontroller assembly code or a C program you directly code the hardware so before sarting VHDL I think someone must know basic things about which code creates which kind of hardware,after that He can write a reasonable vhdl code so before vhdl brush-up lesson I think there should be a lesson which explains the sysnthesis of the VHDL.»
- the subject of the guest lecture»
- Reduce the lab workload, please!»
- More lectures of the labs. This year the first three labs were presented during 30 minutes and the last three during one lecture. Not sufficient!»
- The lab is very hard»
- The labs are not defined well. I could not really understand what is required from me from labs and prelabs in complete detail. There were always some things that are required but not told us to do. If you look this from the one of the project models ie, waterfall, the specifications were not set completely and we were discovering that at the very end. Thus we had to sometimes even iterate from the very beginning. Some kind of Wavefrom can be added to do lab documents to show how the designs should act.»
- Lab structure should change completely. It was a useless lab.»
- The labs, better labmemos are needed. Smaller labs doesnt mean that you learn less.»
- labs workload»
- There should be some part related to high frequency PCB as every electronics system design has to be implemented on a PCB.»
- as i told above,and get from most classmates,the course was based on assuming that the participents have good knowledg of VHDL,but most didn"t!so if there would be additional introduction on vhdl it would be very good!»
- some guest lecture should be changed»
- u can have good lectures on digital filters & VHDL learning. LAB6 is very hard,when i"ve designed the MATLAB file and generate code for ISE , i haden"t any idea what"s this file.just some friends come to me and help me,the funny thing is no one know why we should change something in ISE AMTLAB FILES. »
- Excesive workload in the labs. More information to do the labs.»
- The labs.»

28. Additional comments

- I am happy for learning some useful knowledges.»
- General outline of professional coding could help us.»
- Some of the guest lectures are really inspiring. but I couldn"t get most of the idea. some of the information are not for a new student without knowing much of this field, it could be really helpful for an experienced designer but too soon for me.»
- Lectures was very interesting, but too theoric. Most of the time, after a lecture, I had a lot of idea, but it was very figurative ...»
- There was a file that you put up on the course home page that was about "clock enables" and that file really helped me to get on the right track for synthesis. It would have been nice if we had more of those to suggest tips and tricks for synthesizable code.»
- the course cover too much subjects that I am a little confused.»
- Coordinate the work load with the other course in the study period.»
- You"ve got the right idea and solution to a problem with students with different backgrounds. Teach everyone up to a base point and then we can work from that. The lectures are fine and doesn"t have to be changed. I"ll adress the labs as a completly different cource. The PM should have clearer instructions and or give more hints on to solve the problems. More feedback HAS to be given to solutions and this has to be fixed with more people getting involved with the labs. With comprehensive feedback learning will be faster and students wont be stuck on problems from earlier labs. I"m not the best but not a bad student and I had at times 1-3 labs to review at once when they got done. There"s very hard to find faults with a design when you"re just learning and I would like to have the option to send code for review and then get feedback after each of the labs if you didn"t finish. Looking at code is hard work and this has to be adressed with more people working with the labs more than Sven and Lars. Great was that the labs was open at all times and that you had the option to use the Sparta cards even on weekends and evenings (it was needed) one sunday we were 12 people there working on the same lab at late afternoon... I would look over how many people acctually finished the labs on the appointed time and you will get an indication where there was problems. Good luck»
- The labs were too crowded and noisy. There were only two people (prof. Sven Knuttson and prof. Lars Kollberg) and they could not help us most of the time when we had a question, and in fact as professors they should not bother with every small question students ask. There should be some TAs helping there. But in anyways the definition of the labs should be better.»
- I had the feeling that the lab sessions are good just for a few number of students.»

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